When external power supply in the memory device, such as the DRAM, goes down, a serious problem encountered is the loss of cell signal due to noise in the circuit. The problem may not seriously hazard the performance of the memory device, when the external power supply is much higher than the threshold voltage of the transistors of the memory cell. For example, the external power supply reducing from 12 V to 10 V may not be a problem and still be enough to turn on the transistors of the memory cells through the word-lines. However, when the voltage level of the external power supply is quite close to the threshold voltage of the transistors, the reduction of the external power supply, for instance from 5 V to 3.5 V may cause the memory devices malfunctioned and therefore need to be resolved.
Traditionally, a boost circuit is embedded in the memory device for responsive to control signals to raise the voltage level on the word-lines for compensating the loss of cell signal. An example of the boost circuit was given by Betty Prince .sup.[1] as shown in FIG. 1. Preceding operation, node N.sub.1 is charged to Vcc by clock R and a full charge is stored in capacitor C. Signal IN simultaneously triggers buffers A and B so as to push node N.sub.1 to twice Vcc. Because node B and node N.sub.1 are in the same voltage level, through node B, a boosted signal is provided and the problem of signal loss is overcome.
 FNT .sup.[1] Betty Prince "SEMICONDUCTOR MEMORIES--2nd edition" pp. 235-237.
Another traditional boost circuit includes a number of individual booster active kickers connected to a booster voltage power line, which branches to a group of world-lines down stream, in parallel for generating enough charges to serve the word-lines. An example is shown in FIG. 2 by Kim et al. .sup.[2], The standby booster voltage generator 23 and a number of booster active kickers 15, 17, 19, . . . 21 are connected to the booster voltage power line 13 for responsive to the control signal PR to supply a boosted signal. One advantage of the boost circuit is the high capacitance for boosting. However, in some cases, there may be the shortcoming that pushing the voltage on the word-lines to an unacceptable high level so that resulting in unnecessary power consumption and undesired reliability issues.
 FNT .sup.[2] Kim et al. U.S. Pat. No. 5,867,442.
Kim et al. .sup.[2] proposed another boost circuit with many control signals, which are able to independently trigger the booster active kickers, for providing variable boost ratios in accommodation to various operation states, e.g. clock frequencies, external power supply voltages, etc.. As shown in FIG. 3. The standby booster voltage generator 23 and a number of booster active kickers 15, 17, 19, . . . 21 are connected to the booster voltage power line 13. Control signal PR, booster voltage active control signal PAK, and refresh cycle control signal REF together control the booster active kickers so as to provide variable boosting ratios for the booster voltage power line 13.
 FNT .sup.[2] Kim et al. U.S. Pat. No. 5,867,442.
Although the traditional techniques have merits on control flexibility due to the variable boost ratios, there is a room awaited for further improvement. For example, the booster active kickers are charged by the booster voltage power line when they are at both precharging and boosting mode. That is to say, whatever activated or not, the booster active kickers burden the booster voltage power line, thereby destabilizing the power supply through the booster voltage power line. Moreover, the designs of the traditional techniques are somewhat complicated to be implemented in memory devices. Given the shortcomings of the conventional arts, there establishes a huge need to improve the design of the boost circuit.